This invention relates to a muting circuit and to an FM radio receiver having the muting circuit.
As a muting circuit providing a large signal attenuation, the inventors of the present invention previously proposed a so-called "electronic switching circuit" making use of a differential transistor circuit such as shown in FIG. 1, for example.
In this circuit, collectors of differential amplification transistors Q.sub.1, Q.sub.2 for signal transmission and those of differential transistors Q.sub.3, Q.sub.4 for forming a d.c. signal at the time of muting operation are commonly connected, and constant current transistors Q.sub.5, Q.sub.6 are connected to common emitters of the respective differential transistors Q.sub.1, Q.sub.2 and to those of Q.sub.3, Q.sub.4, the constant current transistors Q.sub.5, Q.sub.6 being selectively and alternately operated by a switch SW.sub.1.
An input signal is applied to the base of the differential transistor Q.sub.1. A bias voltage V.sub.B1 is also applied to the base of transistor Q.sub.1 via a bias resistor R.sub.B, and to the base of the differential transistor Q.sub.3 directly. A negative feedback signal is applied to the bases of the transistors Q.sub.2, Q.sub.4 via a feedback circuit .beta., thereby setting the gain of the differential amplification transistor circuit and providing a d.c. bias voltage.
The circuit operates as follows: When the switch SW.sub.1 is set to side a, the constant current transistor Q.sub.5 becomes inoperative while the constant current transistor Q.sub.6 becomes operative so that the differential amplification transistors Q.sub.1, Q.sub.2 are turned off while the differential transistors Q.sub.3, Q.sub.4 are turned on. Consequently, only the same d.c. signal as the bias voltage V.sub.B1, that is formed by the differential transistors Q.sub.3, Q.sub.4, can be obtained at the output OUT.
On the other hand, when the switch SW.sub.1 is set to side b, the differential amplification transistors Q.sub.1, Q.sub.2 become operative and transmit the input signal IN. Accordingly, a large signal attenuation can be obtained without changing the output d.c. signal.
The inventors of the present invention found that in this muting circuit when the input signal IN is applied via a coupling capacitor C.sub.1 the following problem occurs.
Namely, it is possible to assume that the input terminal IN in FIG. 1 is substantially grounded through the practically negligible impedance of a signal source (not shown), so that the bias voltage V.sub.B1 rises immediately at the time t.sub.1, immediately after connecting the power source as shown in FIG. 2, whereas the voltage V.sub.B1, at the junction between the coupling capacitor C.sub.1 and the bias resistor R.sub.B gradually rises due to the time constant of capacitor C.sub.1 and resistor R.sub.B.
Accordingly, if the switch SW.sub.1 is kept closed to the side a during a predetermined period from the time t.sub.1 to the time t.sub.2, the base voltage of both differential amplification transistors Q.sub.3, Q.sub.4 is equal to the bias voltage V.sub.B1 and consequently, the collector potential of the transistor Q.sub.4 becomes V.sub.B1 /.beta.. Since an output coupling capacitor C.sub.o connected to the output terminal OUT and the impedance of a load (not shown) form a differential circuit together, the waveform obtained by differentiating the collector potential V.sub.B1 /.beta. of the transistor Q.sub.4 occurs at the output terminal OUT at the time t.sub., as depicted in the waveform diagram of FIG. 2. This transient response waveform occurring at the time t.sub.1 eventually results in a popping noise, but can be prevented by arranging a muting circuit (not shown) at a subsequent stage of this circuit.
When the switch SW.sub.1 is switched from side a to side b at the time t.sub.2, the base of the transistor Q.sub.2 is biased by the bias voltage V.sub.B1 whereas the base of transistor Q.sub.1 is biased by the voltage V.sub.B1 ' which is lower than the bias voltage V.sub.B1. Consequently, since a voltage difference .DELTA.V as shown in the waveform diagram of FIG. 2 is applied between the bases of the differential amplification transistors Q.sub.1 and Q.sub.2, the collector potential of the transistor Q.sub.2 drops drastically at the time t.sub.2. The waveform obtained by differentiating this collector potential by the output coupling capacitor C.sub.o and the impedance of the load occurs at the output terminal OUT at the time t.sub.2 as shown in the waveform diagram of FIG. 2.
The inventors of the present invention have found that prevention of the popping noise at the time t.sub.2 can be accomplished by reducing the time constant at the rise of the voltage V.sub.B1 ' to an extremely small value. Accordingly, the inventors examined the idea of reducing the capacitance of the coupling capacitor C.sub.1, but this plan was abandoned because a problem of phase inversion of low frequency signals arises.
Reducing the resistance of the bias resistor R.sub.B was attempted, but this plan was also abandoned because of the lowering of the input impedance at the input terminal IN.
Occurrence of the popping noise due to the transient response waveform at the time t.sub.2 can be prevented by disposing another muting circuit (not shown) at a subsequent stage of this circuit, but when the capacitance of the coupling capacitor and the resistance of the bias resistor R.sub.B are set to about 10 .mu.F and about 40 K.OMEGA., respectively, the muting time of the muting circuit disposed at the subsequent stage of this circuit must be set to as long as about three seconds. If the muting operation is carried out for such a relatively long period after turning on the power source, however, the listener of the radio receiver would think that the radio receiver was out of order.
On the other hand, as one of the additional functions of an FM radio receiver, a muting circuit for eliminating offensive noise between stations during selection of the stations has heretofore been known, as disclosed in "HI-FI FM TUNER", p. 193-199, published on Aug. 20, 1976 by Nippon Hoso Kyokai, for example.
FM radio receivers employing this muting circuit in a monolithic semiconductor integrated circuit for FM intermediate frequency amplification and detection are commercially available from RCA, U.S.A., under the tradename "CA3089E", and from Hitachi Limited, Japan, under the tradename "HA1137W".
FIG. 3 shows a block diagram of an FM radio receiver including the monolithic semiconductor integrated circuit. This radio receiver was examined by the inventors of the present invention prior to the filing of this patent application.
In the drawing, symbol IC.sub.1 represents the monolithic semiconductor integrated circuit for FM intermediate frequency amplification and detection. This integrated circuit includes an FM intermediate frequency amplification stage 1, an FM detection stage 2, a low frequency amplication stage 3, a detuning detection circuit 4, and a mute control circuit 6 for controlling the muting operation at the low frequency amplification stage 3. Additionally, this monolithic semiconductor integrated circuit includes an AFC circuit and a level detection circuit, the output signals of which are used as the input signals to the detuning detection circuit 4. Reference numeral 5 represents a time constant circuit which is disposed for removing high frequency components contained in the detuning detection signal.
Symbol IC.sub.2 represents a monolithic semiconductor integrated circuit for FM stereo demodulation. This integrated circuit includes a pre-amplifier 7, a PLL (phase locked loop) circuit 8 for forming a 38 KHz switching signal synchronous with a 19 KHz pilot signal contained in a stereo composite signal, and a stereo demodulation circuit 9. The stereo composite signal formed by the FM detection circuit 2 is applied to the input of the pre-amplifier 7 via a coupling capacitor C.sub.100 while the stereo demodulation circuit 9 forms stereo demodulated signals L, R of the left and right channels by receiving at its input the stereo composite signal passing through the pre-amplifier 7 and the 38 KHz switching signal formed by the PLL circuit 8.
The monolithic semiconductor integrated circuit IC.sub.2 also includes additional circuits for stereo-monaural detection, selection, display, and the like.
In the above monolithic semiconductor integrated circuit IC.sub.1, the popping noise V.sub.pop originates from the FM detection stage 2 due to changes in the d.c. voltage in the S characteristic curve of the FM detection circuit 2 as shown in FIG. 4 during the muting operation for changing over from tuning to detuning upon detection of detuning.
Accordingly, the inventors of the present invention examined the possibility of providing a muting circuit 10 at the output of the stereo demodulation circuit 9 as the subsequent stage. In such a case, the muting circuit 10 must exhibit fast mute-release timing for shifting from detuning to tuning and retarded mute timing for shifting from tuning to detuning in its muting operation in the monolithic semiconductor integrated circuit IC.sub.1. Since these muting operations are independently controlled, the timings are difficult to set and are highly susceptible to variance of element characteristics.
Moreover, the coupling capacitor C.sub.100 is interposed between the two muting circuits 6 and 10 and causes a time advance of the signal to the subsequent muting circuit, so that it becomes extremely difficult for the subsequent muting circuit 10 to eliminate the popping noise generated in the preceding muting circuit 6.